Read an article today in ARS Technica titled NAND flash gets baked, lives longer that researchers at Macronix have come up with a technique that rejuvenates NAND bit cells by heating them. The process releases the bit cells captive electrons and returns it back to a fresh NAND cell.
As discussed previously in this blog (e.g., see The End of NAND is near, maybe… and What eMLC and eSLC do for SSD longevity) as NAND technology shrinks to smaller transistor diameters, their longevity and durability decreases proportionally. Which means that with denser NAND chips coming out over the coming years, they will become increasingly short lived.
With this new approach and an awful lot of engineering to zap a NAND bit cell with intense heat (800C) can take dead NAND cells and bring them back to life. Apparently this rejuvenation process has been known for some time and had been in use for phase change memory but had not been applied to NAND cells in memory. They were heating batches of NAND cells for hours at 200C but this wouldn’t be very practical in production.
The new NAND memory cells are designed with a resistive heating element on top of them, which when enabled can heat the NAND bit cells beneath them. According to some news reports I’ve read this enables the NAND cell to go from 10K P/E cycles to 100K P/E cycles. And the heat only needs to be applied in occasional pulses to keep cells operating within parameters. As such, it can be used sparingly and not cost too much energy in the process.
Another side effect of heating is that erase cycles operate faster than at normal temperatures, which now adds the possibility of heat assisted NAND cells. Erasure being one of the key bottlenecks to NAND write performance anything that can speed this up would help.
In honor of today’s Flash Summit conference, I give my semi-annual amateur view of competing NAND technologies.
I was talking with a major storage vendor today and they said they were sampling sub-20nm NAND chips with P/E cycles of 300 with a data retention period under a week at room temperatures. With those specifications these chips almost can’t get out of the factory with any life left in them.
On the other hand the only sub-20nm (19nm) NAND information I could find online were inside the new Toshiba THNSNF SSDs with toggle MLC NAND that guaranteed data retention of 3 months at 40°C. I could not find any published P/E cycle specifications for the NAND in their drive but presumably this is at most equivalent to their prior generation 24 nm NAND or at worse somewhere below that generations P/E cycles. (Of course, I couldn’t find P/E cycle specifications for that drive either but similar technology in other drives seems to offer native 3000 P/E cycles.)
Intel-Micron, SanDisk and others have all recently announced 20nm MLC NAND chips with a P/E cycles around 3K to 5K.
Nevertheless, as NAND chips go beyond their rated P/E cycle quantities, NAND bit errors increase. With a more powerful ECC algorithm in SSDs and NAND controllers, one can still correct the data coming off the NAND chips. However at some point beyond 24 bit ECC this probably becomes unsustainable. (See interesting post by NexGen on ECC capabilities as NAND die size shrinks).
Not sure how to bridge the gap between 3-5K P/E cycles and the 300 P/E cycles being seen by storage vendors above but this may be a function of prototype vs. production technology and possibly it had other characteristics they were interested in.
But given the declining endurance of NAND below 20nm, some industry players are investigating other solid state storage technologies to replace NAND, e.g., MRAM, FeRAM, PCM and ReRAM all of which are current contenders, at least from a research perspective.
Recently the PCM approach has heated up as PCM technology is now commercially available being released by Micro. Yes the technology has a long way to go to catch up with NAND densities (available at 45nm technology) but it’s yet another start down a technology pathway to build volume and research ways to reduce cost, increase density and generally improve the technology. In the mean time I hear it’s an order of magnitude faster than NAND.
Racetrack memory, a form of MRAM using wires to store multiple bits, isn’t standing still either. Last December, IBM announced they have demonstrated Racetrack memory chips in their labs. With this milestone IBM has shown how a complete Racetrack memory chip could be fabricated on a CMOS technology lines.
However, in the same press release from IBM on recent research results, they announced a new technique to construct CMOS compatible graphene devices on a chip. As we have previously reported, another approach to replacing standard NAND technology uses graphene transistors to replace the storage layer of NAND flash. Graphene NAND holds the promise of increasing density with much better endurance, retention and reliability than today’s NAND.
So as of today, NAND is still the king of solid state storage technologies but there are a number of princelings and other emerging pretenders, all vying for its throne of tomorrow.
Enterprise NAND from Micron.com (c) 2010 Micron Technology, Inc.
I talked last week with some folks from Nimbus Data who were discussing their new storage subsystem. Apparently it uses eMLC (enterprise Multi-Level Cell) NAND SSDs for its storage and has no SLC (Single Level Cell) NAND at all.
Nimbus believes with eMLC they can keep the price/GB down and still supply the reliability required for data center storage applications. I had never heard of eMLC before but later that week I was scheduled to meet with Texas Memory Systems and Micron Technologies that helped get me up to speed on this new technology.
eMLC/eSLC defined
eMLC and its cousin, eSLC are high durability NAND parts which supply more erase/program cycles than generally available from MLC and SLC respectively. If today’s NAND technology can supply 10K erase/program cycles for MLC and similarly, 100K erase/program cycles for SLC then, eMLC can supply 30K. Never heard a quote for eSLC but 300K erase/program cycles before failure might be a good working assumption.
The problem is that NAND wears out, and can only sustain so many erase/program cycles before it fails. By having more durable parts, one can either take the same technology parts (from MLC to eMLC) to use them longer or move to cheaper parts (from SLC to eMLC) to use them in new applications.
This is what Nimbus Data has done with eMLC. Most data center class SSD or cache NAND storage these days are based on SLC. But SLC, with only on bit per cell, is very expensive storage. MLC has two (or three) bits per cell and can easily halve the cost of SLC NAND storage.
Moreover, the consumer market which currently drives NAND manufacturing depends on MLC technology for cameras, video recorders, USB sticks, etc. As such, MLC volumes are significantly higher than SLC and hence, the cost of manufacturing MLC parts is considerably cheaper.
But the historic problem with MLC NAND is the reduction in durability. eMLC addresses that problem by lengthening the page programming (tProg) cycle which creates a better, more lasting data write, but slows write performance.
The fact that NAND technology already has ~5X faster random write performance than rotating media (hard disk drives) makes this slightly slower write rate less of an issue. If eMLC took this to only ~2.5X disk writes it still would be significantly faster. Also, there are a number of architectural techniques that can be used to speed up drive write speeds easily incorporated into any eMLC SSD.
How long will SLC be around?
The industry view is that SLC will go away eventually and be replaced with some form of MLC technology because the consumer market uses MLC and drives NAND manufacturing. The volumes for SLC technology will just be too low to entice manufacturers to support it, driving the price up and volumes even lower – creating a vicious cycle which kills off SLC technology. Not sure how much I believe this, but that’s conventional wisdom.
The problem with this prognosis is that by all accounts the next generation MLC will be even less durable than today’s generation (not sure I understand why but as feature geometry shrinks, they don’t hold charge as well). So if today’s generation (25nm) MLC supports 10K erase/program cycles, most assume the next generation (~18nm) will only support 3K erase/program cycles. If eMLC then can still support 30K or even 10K erase/program cycles that will be a significant differentiator.
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Technology marches on. Something will replace hard disk drives over the next quarter century or so and that something is bound to be based on transistorized logic of some kind, not the magnetized media used in disks today. Given todays technology trends, it’s unlikely that this will continue to be NAND but something else will most certainly crop up – stay tuned.
Read an article today in ARS Technica titled NAND flash gets baked, lives longer that researchers at Macronix have come up with a technique that rejuvenates NAND bit cells by heating them. The process releases the bit cells captive electrons and returns it back to a fresh NAND cell.
